FDD86326 n-channel shielded gate powertrench ? mosfet ?2010 fairchild semiconductor corporation FDD86326 rev.c2 www.fairchildsemi.com 1 may 2013 FDD86326 n-channel shielded gate powertrench ? mosfet 80 v, 37 a, 23 m features shielded gate mosfet technology max r ds(on) = 23 m at v gs = 10 v, i d = 8 a max r ds(on) = 37 m at v gs = 6 v, i d = 4.6 a high performance trench technology for extremely low r ds(on) high power and current handling capability in a widely used surface mount package very low qg and qgd compared to competing trench technologies fast switching speed 100% uil tested rohs compliant general description this n-channel mosfet is produced using fairchild semiconductors advanced powertrench ? process that incorporates shielded gate technology. this process has been optimized for r ds(on) , switching performance and ruggedness. application dc - dc conversion mosfet maximum ratings t c = 25 c unless otherwise noted thermal characteristics package marking an d ordering information symbol parameter ratings units v ds drain to source voltage 80 v v gs gate to source voltage 20 v i d drain current -continuous t c = 25 c 37 a -continuous t a = 25 c (note 1a) 8 -pulsed 40 e as single pulse avalanche energy (note 3) 121 mj p d power dissipation t c = 25 c 62 w power dissipation t a = 25 c (note 1a) 3.1 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case 2.0 c/w r ja thermal resistance, junction to ambient (note 1a) 40 device marking device package reel size tape width quantity FDD86326 FDD86326 d-pak(to-252) 13 12 mm 2500 units g s d to-252 d-pak (to-252) d g s
FDD86326 n-channel shielded gate powertrench ? mosfet ?2010 fairchild semiconductor corporation FDD86326 rev.c2 www.fairchildsemi.com 2 electrical characteristics t j = 25 c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 80 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 67 mv/c i dss zero gate voltage drain current v ds = 64 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 100 na on characteristics v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 2 3.1 4 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -8.5 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 8 a 19 23 m v gs = 6 v, i d = 4.6 a 26 37 v gs = 10 v, i d = 8 a, t j = 125 c 33 44 g fs forward transconductance v ds = 10 v, i d = 8 a 21 s (note 2) dynamic characteristics c iss input capacitance v ds = 50 v, v gs = 0 v, f = 1 mhz 780 1035 pf c oss output capacitance 180 240 pf c rss reverse transfer capacitance 15 25 pf r g gate resistance 0.4 switching characteristics t d(on) turn-on delay time v dd = 50 v, i d = 8 a, v gs = 10 v, r gen = 6 7.6 15 ns t r rise time 3.0 10 ns t d(off) turn-off delay time 13.4 24 ns t f fall time 2.9 10 ns q g total gate charge v gs = 0 v to 10 v v dd = 50 v, i d = 8 a 13.4 19 nc q g total gate charge v gs = 0 v to 5 v 7.6 11 nc q gs gate to source gate charge 4.0 nc q gd gate to drain miller charge 3.7 nc drain-source diode characteristics v sd source to drain diode forward voltage v gs = 0 v, i s = 8 a (note 2) 0.8 1.3 v v gs = 0 v, i s = 2.6 a (note 2) 0.7 1.2 t rr reverse recovery time i f = 8 a, di/dt = 100 a/ s 43 68 ns q rr reverse recovery charge 43 68 nc notes : 1. r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the s older mounting surface of the drain pins. r jc is guaranteed by design while r ja is determined by the users board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. starting t j = 25 c, l = 3 mh, i as = 9 a, v dd = 80 v, v gs = 10 v. a. 40 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 96 c/w when mounted on a minimum pad of 2 oz copper.
FDD86326 n-channel shielded gate powertrench ? mosfet ?2010 fairchild semiconductor corporation FDD86326 rev.c2 www.fairchildsemi.com 3 typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 10 20 30 40 v gs = 6 v v gs = 10 v v gs = 5 v v gs = 4.5 v pulse duration = 80 s duty cycle = 0.5% max v gs = 8 v i d , drain current (a) v ds , drain to source voltage (v) on-region characteristics figure 2. 0 10203040 0 1 2 3 4 5 6 v gs = 4.5 v v gs = 8 v normalized drain to source on-resistance i d , drain current (a) v gs = 10 v v gs = 6 v v gs = 5 v pulse duration = 80 s duty cycle = 0.5% max n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i d = 8 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 46810 10 20 30 40 50 60 70 80 t j = 125 o c i d = 8 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m ) pulse duration = 80 s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 234567 0 10 20 30 40 t j = 150 o c v ds = 5 v pulse duration = 80 s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 50 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDD86326 n-channel shielded gate powertrench ? mosfet ?2010 fairchild semiconductor corporation FDD86326 rev.c2 www.fairchildsemi.com 4 figure 7. 03691215 0 2 4 6 8 10 i d = 8 a v dd = 50 v v dd = 25 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 75 v gate charge characteristics figure 8. 0.1 1 10 80 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 10 30 1 2 3 4 5 6 7 8 9 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 10 20 30 40 r jc = 2 o c/w v gs = 4.5 v v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e operating area 1 10 100 200 0.1 1 10 100 dc 100 ms 10 ms 1 ms 100 us i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r jc = 2 o c/w t c = 25 o c figure 12. 10 -5 10 -4 10 -3 10 -2 10 -1 1 10 50 100 1000 10000 v gs = 10 v p ( pk ) , peak transient power (w) t, pulse width (sec) single pulse r jc = 2 o c/w t c = 25 o c s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25 c unless otherwise noted
FDD86326 n-channel shielded gate powertrench ? mosfet ?2010 fairchild semiconductor corporation FDD86326 rev.c2 www.fairchildsemi.com 5 figure 13. junction-to-case tran sient thermal respo nse curve 10 -5 10 -4 10 -3 10 -2 10 -1 1 0.01 0.1 1 single pulse r jc = 2 o c/w duty cycle-descending order normalized thermal impedance, z ja cg s o() d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c typical characteristics t j = 25 c unless otherwise noted
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